FPGAs are quite fast and can switch up to 200 or even more MHz. But when it comes to PWM we have a problem: even at high clocks we cannot create a high resolution as with increasing bits of the digital signal (24 bit audio for instance) we would need a clock above 1 GHz…
The following code was written by Petr Nohavica in 2009 and receives a stereo-signal from an AES3 or AES/EBU receiver which is known as S/PDIF as well:
The following code takes some of the 24 bits of an audio-signal and outputs an 8-bit vector that can be used for a simple VU-meter or brightness control:
This is the logic for a nice stereo S/PDIF transmitter:
In 2024 I spent some time to find a good solution to convert digital audio to analog signals. I ended up using different types of sigma-delta-modulators with different orders and tested multiple configurations. The following implementations contain the most promising solutions for the Class-D-Amplifier we built up at the University of Kassel in 2024 for…
To prevent crackling, hissing or other disturbing signals when no usable signal is at an ADC-input, we use noisegates to keep noise out of our audio-mix. The following snippet shows a stereo-noisegate with adjustable threshold, range-control and adjustable coefficients for attack, release and hold. The calculation of these coefficients can be found down below. For…
The following code processes an incoming stereo-audio-signal and a prepared mono-sub-signal and calculates a crossover with 24dB for the top- and sub-output. The calculation of the coefficients can be found down below. Please have a look at my X/FBAPE-project at GitHub: https://www.github.com/xn--nding-jua/xfbape The coefficients can be calculated like this:
The following logic is a stereo biquad IIR filter to calculate low-pass, high-pass, notch, band-pass or peak-filters with a very low latency. It uses 13 clock-cycles to calculate a stereo-signal and at 100MHz the block is ready after 130 nanoseconds. The calculation of the coefficients can be found down below. Have a look at my…
To control one or more DMX512 universes from an FPGA, the following snippet outputs an USITT compatible DMX512 output-stream. The DMX512 timings can be adjusted using the generic-parameters. The standard timing-parameters are: Description Parameter Breaktime (t_min) 88 µs Mark after Break 8 µs Inter-Byte-Time 0 µs Mark before break time 0 µs Refresh-Rate 44 Hz…
Todays microcontrollers are already capable of processing real-time audio. But if you want to bring down the latency as low as possible, you can use an FPGA – its even faster than modern DSPs that typical use several samples as buffer. The following logic contains a stereo dynamic compressor with controllable threshold, ratio and makeup-gain….
