The following code processes an incoming stereo-audio-signal and a prepared mono-sub-signal and calculates a crossover with 24dB for the top- and sub-output. The calculation of the coefficients can be found down below. Please have a look at my X/FBAPE-project at GitHub: https://www.github.com/xn--nding-jua/xfbape The coefficients can be calculated like this:
The following logic is a stereo biquad IIR filter to calculate low-pass, high-pass, notch, band-pass or peak-filters with a very low latency. It uses 13 clock-cycles to calculate a stereo-signal and at 100MHz the block is ready after 130 nanoseconds. The calculation of the coefficients can be found down below. Have a look at my…
To control one or more DMX512 universes from an FPGA, the following snippet outputs an USITT compatible DMX512 output-stream. The DMX512 timings can be adjusted using the generic-parameters. The standard timing-parameters are: Description Parameter Breaktime (t_min) 88 µs Mark after Break 8 µs Inter-Byte-Time 0 µs Mark before break time 0 µs Refresh-Rate 44 Hz…
Todays microcontrollers are already capable of processing real-time audio. But if you want to bring down the latency as low as possible, you can use an FPGA – its even faster than modern DSPs that typical use several samples as buffer. The following logic contains a stereo dynamic compressor with controllable threshold, ratio and makeup-gain….
Next to the TDM transmitter this VHDL-logic will receive 8 audio-channels and output them as 24-bit vectors:
This is an implementation of an 8-channel TDM-transmitter that accepts 24-bit audio, but transmits it within a 32-bit TDM-stream:
An FPGA is a very universal device – if you need a specific digital serial interface, you simply build it on your own. Here is a SPI-interface, that transmits 16 bits, 8 bit for the address, another 8 bit for the data. It is very useful to configure devices like a SPI-ADC, DAC or other…
This is the VHDL-logic to transmit 8 individual channels via a single digital transmission line. UltraNet uses an AES3-like connection that contains some Behringer specific channel-status-data. For longer transmission-lines a differential transceiver should be used. Important side-note: even the VHDL-block will take 24-bit audio, UltraNet uses the least-significant two bits to transmit an information for…
Dealing with digital audio is a nice thing. Here is my implementation of a 2- and 8-channel I2S-Receiver: If you want to deal with multiple I2S ADCs that are connected to the same bit-clock and frame-sync, we can receive multiple channels at once:
While reverse engineering the Behringer P16-I I’ve found a nice thing: this devices has 32 individual LEDs at the front to display the audio-level and the clipping of a channel. But from the internal FPGA only three lines are connected to the front-leds. So I hooked up an oscilloscope and found out, that the signal…
