6-phase Clarke transformation
To convert a 6-phase signal into a 90° system, the following logic can be helpful:
6-phase Inverse Clarke transformation
I had a special BLDC motor with 6 phases. To control the motor with a field-orientet control (FOC) I had to implement a 6-phase conversion from a 90° alpha/beta system into a 6-phase system. The performed equations look like this: So, the alpha/beta signal is transformed into a 6-phase signal. This is a special case…
Park transformation
To convert a 90° system (alpha/beta) into a dq-system, the Park-Transformation is performed. The alpha/beta signal is converted together with a synchronious signal theta to perform the following equation: The alpha/beta signals are usually the result of a Clarke transformation and are used in Field-Oriented Controls (FOC) or Phase-Locked-Loops (PLL). The usual signals look like…
Sin-/Cos-Generator (Mini-Cordic IP-Core)
For both microcontrollers and FPGAs its quite challenging to calculate sine- and cosine-values with good enough precision to calculate different things with higher accuracy. Mitu Raj and Roshan Raju implemented a nice Mini-Cordic-IP-Core that does exactly this: calculate sin/cos as fixed-point values that can be used within an FPGA.
Inverse Park transformation
The following logic performs an inverse park transformation and converts dq-components into alpha-beta-components. It uses the cordic implementation of Mitu Raj that supports angles between -360° and 360°. The implementation can be found in another snippet on this website.
PI-Controller
The following logic contains a standard PI-controller
PWM Deadtime Generator
This logic allows to inject a deadtime to an input-signal. The deadtime can be set in clocks, so the absolute deadtime is depending on the used clock:
Second-Order Generalized Integrator (SOGI)
Disturbances in measured signals for voltage or current are a bit annoying. This file contains a Second Order Generalized Integrator to filter a sine-wave at the input to a disturbance-free output. As replacement for the regular integrator it uses a special third order integrator implementation suggested by Theodorescu et. al. It reduces the ripple on…
PWM with Noiseshaping
FPGAs are quite fast and can switch up to 200 or even more MHz. But when it comes to PWM we have a problem: even at high clocks we cannot create a high resolution as with increasing bits of the digital signal (24 bit audio for instance) we would need a clock above 1 GHz…
S/PDIF receiver
The following code was written by Petr Nohavica in 2009 and receives a stereo-signal from an AES3 or AES/EBU receiver which is known as S/PDIF as well: