Together with some students and a colleague I took part at the International Future Energy Challenge (IFEC) in 2024. It was a great opportunity to combine my interest on power-electronics, audio-technology and microcontrollers. The topic of this competition was to create a Class-D-Amplifier with three channels and 135W output-power – per channel.

Table of Contents

• Origin of the idea
• First ideas and hardware-tests
• First tests with audio
• Simulations of the hardware
• First demonstrator and the semi-finals in Los Angeles
• Schematics and filter design
• Final demonstrator
• Competition in Austin, Texas
• Holidays and afterglow in Germany

Origin of the idea

Class D amplifiers were first invented in the 1950s by British scientist Alec Reeves and given their name in 1955. Their development was later driven forward by further advances, such as those made by Bruno Putzeys at Philips in the 1990s, and by innovations from the US company Tripath with its T amplifiers. So obviously this is not a very new technology, but as this idea is based on switching semiconductors, we can make use of newest semiconductors, to optimize the size and volume of the system. Therefore, we were pleasantly surprised as the IFEC-team published the topic of the year 2024: a Class-D-Amplifier with the following parameters:

So the input voltage of 48V allowed us to think about low-voltage GaN-devices with 60V to 100V blocking-voltage that would allow us high switching-frequencies at low losses. As we all had experience with 50Hz sine-waves for grid-connected PV-inverters, but not with multi-hundret-kHz converters up to the MHz-range this was a quite new task for us. As the human ear is able to hear up to 16kHz – sometimes a bit beyond this limits – it was clear, that we have to deal with switching frequencies around 400 to 800kHz, but in the end we went up to 10 MHz and therefore exceeded the limits we got used to.

First ideas and hardware-tests

OK, what are the first steps on such a journey? First we had to get an idea what type of circuit we want to use. As there are plenty of different approaches to create a Class-D-Amplifier, we selected a topology, that was well known for us: a single-phase inverter:

In this topology the switches T1 and T4 are switched on at the same time, while T2 and T3 are switched off and vice versa. With the correct modulation of this switching signals a current is set to the output filter that acts as a low-pass-filter to restore the original input signal at a much higher voltage to move the dome of the speaker.

The typical way to implement a Class-D-Amplifier is to use an analog part that modulates the input signal together with a feedback from the output and creates a control-signal for the semiconductors. But our plan was to create a fully digital system to have all degrees of freedom using a software- and logic-based approach by using a combination of a microcontroller and an FPGA. With this design we tried to mitigate the inner digital to analog conversion. As in the original topic-description the playback of “high quality audio 24-bit WAVE-files” was mentioned, we thought this would be the best approach to meet all requirements.

So after a couple of weeks we came to the conclusion, that we would use an FPGA for the high-speed signals like Audio-ADC via I2S, some EQs via IIR-biquad-filters directly in logic as well as the modulation for the control-signals for the GaN-bridge. A microcontroller should be used for the calculation of the EQ-coefficients and the SD-card-playback – and maybe bluetooth, so we had the ESP32 in mind. After reading lot of different publications on Class-D-Amplifiers, we planned a feedback-loop to implement a control-loop to compensate non-linear-parts of the filter and the connected speaker lateron. This was one of our sketches:

The final plan of the control-loop looked like this:

But first of all we had to find a good solution to control the hardware with an appropriate control-signal. It turned out, that there are two promising strategies to control a Class-D-amp: PWM or PDM. PWM, or Pulse-Width-Modulation, is a common method to control the brightness of LEDs or the speed of fans, or even motor-inverters. But the pulse-density-modulation looked more promising to be implemented in the FPGA as it used a simple sigma-delta-modulator that was quite simple to implement in VHDL. A PWM modulator would make use of a high-speed counter-signal that would need tens or even hundrets of MHz to allow a proper conversion of a multi-bit-audio-signal. Since we had planned to use at least 24-bit audio, this did not seem to be a solution.

By comparing the PDM with the PDM signal, you can see that the PWM offers a continuous switching-pattern while the PDM has parts especially at high or low signals with no switching at all. So we planned to make use of this shifting of switching-losses to parts, where the current is low, resulting in less switching losses for a better overall performance.

First tests with audio

As we were all power-electronics engineers – or at least students in this field of study – we had no experience with high-quality audio-processing. In winter of 2023 we made our first steps using impedance measurement device to get in touch with audio-processing using some eval-boards for the PCM1820 ADC together with an Arduino Vidor 4000 board containing an Intel Cyclone 10LP FPGA, an ESP32 and a SAMD21 Cortex M0+ microcontroller:

With this setup we were able to implement some basic EQing, volume-control and basic audio-mixing using just the FPGA and the ESP32. This was the time were I’ve written an article for the Elektor magazin about my experiences on FPGA audio-processing in 2023. Using the Bode100 device we could validate the audio-processing using some EQs:

OK, but measuring is one thing, processing and outputting real audio is another thing. So we hooked up some active speakers on a S/PDIF-converter, connected our FPGA-board to it and heared audio through our test-board for the first time:

As a side project, some of the students created a webinterface to control the whole system without a computer:

We also implemented and tested some basic audio-filters like low- and high-pass-filters for the planned crossover to drive the tweeters and subwoofer with filtered signals. Both filters worked quite well. Here you can see the lowpass-filter in action, using a sinewave-generator. The lowpass is set to 150Hz and uses 24dB per octave:

Now that we gained some experiences with audio-processing, we started creating some power-electronics simulations using the software PLECS made by the swiss company Plexim to get an idea of possible solutions for the real hardware of the Class-D-Amplifier.

Simulations of the hardware

So we implemented the main-GaN-bridge together with the most important parts of the PDM and the output-filter into the software PLECS:

On the left side several different input-signals could be selected, like a simple sinewave, an overmodulated multi-sine-wave audio-signal or a converted WAVE-audiofile, imported as a large CSV-table. In the orange part we had the option to use the direct signal or an upsampler realized using a low-pass-filter sampled at 4.8MHz. The red part contains the sigma-delta-converter. On my blog you can find some example VHDL-snippets of different sigma-delta-modulators. The Class-D-power-stage is shown in the black-area followed by the outputfilter in blue and a simple resistor-load or a model of a speaker in the red area.

First we tried implementations of sigma-delta-modulators of different orders with different filter-options to find the best performing type. Here you will find an excerpt of four different sigma-delta-modulators with different types of noise-shaping:

Once we had a good idea of how the modulators are working and what type of filter we would have to use, we started looking at some audio. As WAVE-files are actually just a series of individual audio samples strung together, we could feed the power-electronics simulation with such audio-snippets. First here is a regular wave-file opened in GoldWave:

And here is the same snippet in our power-electronics simulation:

We were very satisfied when we had a working plan for the implementation – at least in the simulation. Now that the this was looking fine, we had to go the next step and create a schematic and the layout for our PCB to test the system in the real world.

First demonstrator and the semi-finals in Los Angeles

We’ve decided to use a two-step approach: first create a laboratory demonstrator on a single PCB to test all components and create a second iteration with much less volume for the final demonstrator. The first demonstrator was ready right before the semi-finals in LosAngeles in spring of 2024:

The semi-finals took place in LongBeach in Los Angeles, California. It was a great time at the APEC2024 (picture on the left) and visiting Hollywood, Universal Studios – and of course the Paramount Studios (picture on the right) as I’m a Trekkie since I’m 6 years old!

Schematics and filter design

We returned from the semi-finals in march 2024, but unfortunately lost some drive after the semi-finals and stopped working for a couple of weeks on this topic. We didn’t continue until end of may 2024 with the final demonstrator. Keeping in mind that our journey to the USA started at 11th of July, we began working on the PCBs on mid of June – as I said, a bit late. But the students did a great job and created a very good looking amplifier- and control-board. Our idea was to use a single PCB per channel and a main-control-PCB above these three PCBs. As we’ve planned a switching frequency of around 4 to 5 MHz, we used the TI UCC21520ADW gatedriver, that is specified for up to 5 MHz and has built-in deadtime generators for a single half-bridge:

We were aware, that the output filter was crucial for a good performance, so we spent some time on figuring out the right components. The general filter-design was quite simple as TI had an Excel-Sheet to calculate the desired values for a specific cut-off frequency and a specific load. We desired a cut-off-frequency between 20kHz and 25kHz and have chosen a ceramic capacitor of 470nF. We looked for special inductors that would still function as inductors even at several MHz and found special devices by Coilcraft. So in the end we found the following filter-design:

The schematics of the filter are quite simple:

As previously said, the selection of the inductor was quite tough. First we tested some inductors we’ve found at the university. But while increasing the frequency, the device did not behave like an inductor anymore. We took a Bode-100-Analyzer and investigated the devices and realized, that it is quite tough to find an inductor for several MHz. In 2024 Coilcraft released a new set of shielded power inductors with the XAL50xx-series. Here we’ve found the XAL5050-series that had a good behaviour over the frequency:

The only problem was, that these types of inductors were published on the PCIM2024 and not available on the distributors yet. So we requested some samples and selected the 22µH and 15µH series. Due to the disturbances in the output we’ve selected the 22µH version and put two of the in series to realize the 44µH filter-inductor shown in the TI filter-design-sheet above. We were aware, that with this inductor we could have a problem at higher currents:

But we ran out of time for more tests and better components. So we stayed with this selection and hoped for the best.

Final demonstrator

On 1st of July we received the PCBs and could start soldering. Have a look at my youtube-video about this very busy periode :). Here is the result of one of the amplifier-boards:

On the left side there are four DIY-transformers for our series-resonant-converter to supply the gate-drivers of the GaN-switches. On the middle part you can see the four GaN-switches together with the four output-inductors. On the right side we placed the DC-link capacitors to buffer the energy for high dynamic audio-signals. The control PCB contained the ADCs, the mic-preamps, the microcontrollers and the FPGA:

We added an OLED display to control the parameters like crossover-frequency, the selection of the SD-card-files and the volumes of all three channels:

While testing the final product we faced several issues, some of them quite severe. So due to the time pressure we missed to place an EEPROM on to the control-PCB. So at first we were not able to upload the FPGA-bitstream to the FPGA. We found a solution on 5th of July by using the onboard SAMD21 with an USB-connection to emulate the USB-Blaster-protocol for the Intel Cyclone 10LP. Wow, at least we were able to upload the logic using a computer. We also had some issues with dropping voltages at the 3.3V rail that caused the FPGA to reset. But with some additional capacitors and a new LDO we solved this problem as well. A tricky problem was the PDM. We realized, that we had problems with disturbances that we did not hear on the first prototype. But we were ultimately able to fix that too by adjusting the modulation. On the left you can see that the modulated current has some problems in the area of the zero-crossing. We could hear these disturbance quite direct. The better approach with an optimized modulator solved this issue on the right side:

The time was up on Wednesday, the 10th of July and without any further tests we put everything together at 5 P.M.. The final construction looked like this:

I did some last cleanup on the laboratory but as my train left on the next day at 4 A.M. I spent the night in my office – not very comfortable, but better as missing the train the next day as my home is 44km in the south of the University. So the next day came and we flew to the USA on 11th of July 2024…

Competition in Austin, Texas

As well as in L.A. it was a great time in Austin, Texas. We had a nice stay at the University of Texas at Austin and had some time to get in touch with the individual devices for the planned tests. But then the final tests were scheduled. We already knew, that our PDM might have some problems as we could not get the control-loop up and running in time. So we were working only with an open-loop device with some bad efficiency due to some problems on our power-supply of the gatedrivers. But anyway, our amplifier worked in general. The team set up the amplifier and together with some experts from Cirrus Logic our team did a very good job here:

The cross-over performed very nicely and showed the expected curve:

But due to the missing control-feedback the THD+N had some severy issues, resulting in a value around 2% only. This means that the amplifier’s interference is so strong that you can even hear it:

After the electrical tests the hearing-tests were scheduled. So we moved to a studio-room where the amplifiers of all teams had to be tested in detail. We had some smaller issues with our input-stage as we set the input-gain a bit too high but overall these tests were quite OK. Unfortunately, other devices were much better than our THD+N with 2%, some were even below 0.001% – so congratulations on this achievement!

Holidays and afterglow in Germany

After staying a couple of days in Austin I moved to Washington D.C. and spent a week in the capital city of the USA. On both stays in the USA I had an interesting and nice time and my highlight in Washington was the visit of the original NCC1701 in the Smithsonian National Air and Space museum:

On my travel back to Germany I had some free time at the airport. So I thought about the issue with the feedback-loop and the overall modulation and implemented a different control-algorithm using a PWM instead of a PDM. We mitigated PWM because of the problem that high-bit-width PWM will demand a high-speed counter. So I used an approach with a 200MHz logic together with only a 6-bit PWM. As we have a 24-bit audio-signal I used a dedicated noise-shaper to reduce the audio from 24-bit down to a 6-bit audio-stream feeding my PWM-block.

For the noiseshaper I’ve found a nice paper with the title “Accurate stability prediction of single-bit higher-order delta-sigma (Δ-Σ) modulators for speech codecs” (https://ieeexplore.ieee.org/document/5937891) where the authors suggested some coefficients, that worked very well for me. A noise-shaper is similar to a sigma-delta-modulator with a higher-order. In this case I’m using a 4th-order modulator like shown in the following diagram by J. Lota et. al.:

I arrived Germany on Tuesday the 23rd of July and went straight to the lab. I connected the amplifier, uploaded my prepared new bitstream and… what can I say… the amplifier sounded GREAT! Unbelievable, if we would have spent only a couple of days more, we could have achieved a much better ranking. But anyway, I’m pretty proud of the things we have achieved so far. Have a look at this wonderfule sine-wave-voltage measured at the output of the amplifier connected to a resistance:

I used MatLAB to calculate the THD+N for this waveform and got this result:

So in the end our amplifier has reached a THD+N-value of 0.247% – much better than the 2% during the competition. This is the moment I heard the amplifier with the optimized control-strategy for the first time:

I spent at least an hour in the lab listening to different types of music on the amplifier, but then the jet lag kicked in and I had to rest. More than one year later, in november 2025 I had the chance to get the amplifier be tested by another person who has lot of experience in the field of audio-technology. He attested us a good sounding and well designed amplifier. On one of his own Class-D-Amplifiers he added a fast diode to the outputs of the amplifier-bridge and could so decrease the THD+N from 0.27% on his measurement to astonishing 0.16%. So this could be an option on our amplifier as well.

Its unbelievable that time flies by and this journey already has ended more than a year ago, but I like to think back to that time: challenging, stressful, educational, depressing, but shortly afterwards enthusiastic again. Thanks to all team-members for this nice journey!

OK, you reached here and haven’t left, so I have some more pictures of our PCBs four you:

…and the signal-paths of the whole structure looked like this:

OK, that really is the end now, thanks for being here!